Introduction

This application analyzes parasitic resistance and EM/IR effects in arbitrary multi‐layer interconnects of integrated circuits (ICs) using advanced matrix‐based techniques.

Circuit and layout designers can assess fundamental metrics—such as point‐to‐point and point resistances—and derived analog phenomena like voltage and current distributions under idealized electrical stimuli.

The interactive, text‐based workflow within a unified layout–simulation environment makes it easier to evaluate and optimize existing interconnect or new variants against target metrics, without the need for time-consuming sidesteps into third-party tools. Once a concept meets specifications, it can be handed off for final implementation and verification.

Key elements:

New and improved functionalities will be part of future updates.

This application is an exploratory tool and does not perform physical verification in any way. Users are responsible for validating layouts using external tools.

Interconnect Composition

Two primary shape types, rectangle (R) and taper (T), can be used throughout the Compose text area. Both have a concise syntax that is checked in real-time:

R[*] layername dx dy 
[ x y ] 
[ ARR rep_x rep_y spacing_x spacing_y ] 
[ N< | N> | N<Vfloat | N>Vfloat | N<Ifloat | N>Ifloat ] 
[ E< | E> | E<Vfloat | E>Vfloat | E<Ifloat | E>Ifloat ] 
[ S< | S> | S<Vfloat | S>Vfloat | S<Ifloat | S>Ifloat ] 
[ W< | W> | W<Vfloat | W>Vfloat | W<Ifloat | W>Ifloat ]



T[*] layername dx_bot dx_top dy 
[ x y ] 
[ ARR rep_x rep_y spacing_x spacing_y ] 
[ R90 | R180 | R270 | MX | MXR90 | MY | MYR90 ]

Any shape must be confined within a single line, with relevant specifications:

Boldfaced shape arguments are keywords:

Only rectangles (R) can have input (= origin) or output (= destination) ports. Comment lines start with //.

The built-in syntax checker toggles the Compose window background to green when the syntax is verified as correct.

Layout Visualization

All valid shapes are drawn in real-time in the Layout area with no predefined color per layer. Layer colors depend on the stream and datatype numbers assigned automatically in the GDSII property table. This can vary per composition but may be adjusted manually by the user.

Further there are visual indications of:

Layer and via visibilities can be switched on or off in the Layout plot legend.

Technology Data

Layer-specific property tables are created dynamically in the Technology Parameters field based on the input layout composition. The tables must be completed with actual technology process data in order to obtain reliable simulation results. Generic placeholder values are present in a first composition.

Most important are the process-specific sheet resistance R□ per layer (in diagonal table fields) and the inter-layer via resistance Rvia (in off-diagonal table fields).

Interconnect Wire Model

An interconnect wire can be described as a 3D rectangular cuboid with a width W and length L when viewed from the top. This view is the engineer’s perspective when drawing IC layout. The cuboid cross section is W . t, with t the process-specific thickness of the wire. Sheet resistance R□ of the wire material equals ⍴ / t where ⍴ is the material resistivity (in Ωm). Wire materials can be copper, aluminum, etc. depending on the process specifics. Typical and min-max sheet resistances per technology layer are available in the design rule documentation that is provided by the foundry.

The point-to-point resistance between two ends of a straight wire equals R□ L / W. This equation is simple and convenient for hand calculations: the engineer simply has to count the “number of squares” L / W. However, this quickly becomes inaccurate in more advanced layout, where wires can have complex geometries that are connected across several layers and with multiple origin and destination points.

The point resistance in the geometrical center of the same straight wire can be roughly approximated by R□ L / 4W when its two ends are driven by voltage sources. It is close to zero near a voltage source. When only one side is driven by a voltage source, the point resistance is maximal at the other side and roughly equals the wire’s point-to-point resistance. Values become unpredictable by hand when moving away from the center or end point in these two cases.

Solver Methods

The tool overlays each shape with a uniform Cartesian grid of which the grid spacing preserves all shape detail in the calculations. The user can choose to further refine this grid or to define a custom uniform grid spacing. It is discouraged to use a larger grid spacing than the one initially suggested by the tool because that would introduce a high risk of losing shape detail and/or simulator malfunction altogether. Finer grids will typically yield more accurate simulation results at the expense of CPU time and memory usage.

Custom-built direct solvers are available in two types:

The Type-I solver automatically transitions to Type II for specific shapes, based on approximate memory usage projections.

Via Formation

Inter-layer connections are made with vias of fixed size, spacing and resistance, usually as many as the overlap region between two layers allows. In this application the user does not draw them physically in the layout composition. Instead via regions are formed automatically based on:

A connectivity group consists of a set of input text lines (in the Compose text area) that are not interrupted by empty lines. When one or more consecutive empty lines are inserted between regular R or T shape lines, different connectivity groups emerge. Overlapping shapes originating from different connectivity groups will not be connected by vias, even if their layers would be marked as ‘connectable’ in the layer stack specification in the Technology Parameters field.

Comment lines do not cause separation into connectivity groups.

During via formation the tool calculates the maximum number of vias that fit in the overlap area, based on the provided technology data (‘Dimension’ property). Their combined resistance is then either distributed and proportionally allocated to every grid node in the overlap area (simulator option ‘Distributed’), or concentrated in a single center-most node (simulator option ‘Reduce to single’).

Simulation Metrics

Point-to-point resistance is the equivalent resistance from the set of input ports towards the set of output ports. It is independent of voltage or current stimuli (they are ignored in this calculation). Since ports are currently attributed to shape edges only, it is in fact an edge-to-edge analysis.

Point resistance is the equivalent resistance from each grid point towards all virtually inactivated port sources: every source is replaced by its idealized internal impedance. Point resistance is a spatially distributed metric that gives insight into areas of resistance buildup. It is a static property of the layout topology and therefore unrelated to actual current flow. Point resistance cannot easily be related to point-to-point resistance, except in very basic shape constructions as illustrated earlier.

Voltage distribution produces a voltage heatmap based on the applied port stimuli (implicit or explicit).

Current distribution produces

Normalization references for current densities are displayed in the heatmaps. Volume current density relies on material resistivity and is therefore dependent on temperature.

Wire efficiency is a dimensionless metric that highlights zones where the user can most effectively improve the layout, should lower peak current or reduced point-to-point resistance be desired. This heatmap emphasizes the least efficient zones.

Interoperability – KLayout

The “Load File” button in the Compose window allows importing either an existing shape file or an XML output file from KLayout’s excellent Net Tracer module.

From KLayout:

  1. choose “Tools → Trace Net” from the menu bar

  2. in the “Net Trace” window, click the “Trace Net” button

  3. click the net of interest in your layout – it highlights the net throughout the hierarchy

  4. in the “Net Trace” window, click the “Export To Text” button and save the file

From this app:

  1. load the saved XML file

  2. add ports and stimuli

Be aware that the KLayout route expects a valid technology setup in that tool. Otherwise there is no connectivity information for its Net Tracer module to work with (at best there is only single-layer tracing). I encourage the user to test/debug this flow using layouts from open-source PDKs that are available via the KLayout Package Manager.

Currently this app has basic support for the SkyWater SKY130 manufacturing process (details at https://skywater-pdk.readthedocs.io). SKY130 layer names may differ between the online documentation and effective implementation in the KLayout PDK. We could identify the following names being used in XML export (or their GDS number pair counterpart): “li”, “poly”, “licon”, “mcon”, “met1”, “met2”, “met3”, “met4”, “met5”, “via1”, “via2”, “via3”, “via4”. Whenever your composition layer set (created or imported) matches these names (case sensitive !), the SKY130 process option is unlocked.

It is always possible to use the “Custom” process option, giving full user control over technology parameters.

Known Limitations

  1. All layer property radio items in the Technology Parameters field must be visited manually (especially after any layer connectivity change) to ensure correct simulation afterwards.

  2. The heatmap filter (rangeslider) does not align well when the browser window size is modified. Alignment is now somewhat optimal for 2K screen resolutions (QHD).

  3. Holes in shapes (= slots) are for now prohibited for calculations.

  1. With the Type-II solver:

  1. The internal calculation of maximum number of vias in a via region assumes a zero extension of the routing layer overlapping a corner or edge via. Usually this extension is a (small) positive number.

  2. When the width or height of a shape divided by the grid spacing is not an integer, small offsets between shape outlines and result heatmaps may be observed. This is due to suboptimal grid covering of the shape. These offsets become smaller for decreased grid spacings.

  3. A custom set of technology parameters can not yet be saved to file.

Acknowledgement

I am grateful to Jean Beeckman for his inspiring work in mathematical modeling and his continued support over the years. His contributions have sparked my interest and curiosity and laid a strong foundation for my own endeavors. I also thank Plotly Cloud for granting early access to their servers.

Copyright – Terms of Use

This application is provided for informational and exploratory purposes only. All calculations and visualizations are generated automatically and may contain inaccuracies. The author makes no guarantees regarding the correctness, completeness, or suitability of the results for any specific purpose.

By using this application, the user acknowledges and agrees that:

Use of this application implies acceptance of these terms.

Copyright © 2025 Gerd Beeckman. All rights reserved.

Contact

This app is a slowly evolving project. If you like it, find bugs, have concerns or ideas for improvement, or want to collaborate, I’d be happy to hear from you. Just find me on LinkedIn.